Design of a New Low Power XOR-XNOR Circuit with Improved Noise Immunity

Authors

Abstract

Abstract __ Due to the main role of XOR-XNOR gates as the building blocks of many basic arithmetic circuits such as multiplexers,
full adders, compressors etc, new methods of improving the speed and power consumption performance has been
reported. As the dimensions have been reduced to deep submicron scale, noise immunity has also become an important
parameter along with speed, power consumption and size. Herein, the functional properties of a number of these XORXNOR
gates are compared and a new low power XOR-XNOR gates with improved noise immunity XOR-XNOR gates
using 10 transistors is proposed. In passive defense issues, the immunity to electromagnetic disturbances is of
paramount importance. Therefore increasing the circuits’ immunity to noise will help the circuits’ function properly
against electromagnetic disturbances. The simulation results with 0.18(μm) technology in an Hspice software for all
supply ranges from 0.6(V) to 3.3(V) has shown that the new proposed circuit has lower power consumption, an
improved PDP with better noise immunity compared to the previous reported circuits.

Keywords


Volume 3, Issue 2 - Serial Number 8
November 2012
Pages 95-102
  • Receive Date: 30 January 2019
  • Revise Date: 25 November 2024
  • Accept Date: 30 January 2019
  • Publish Date: 22 July 2012